1. Field of the Invention
The present invention relates to two-wire input/output devices and specifically to a LAN transceiver for transmitting/receiving on LAN transmission lines.
2. Description of the Background Art
FIG. 40 is a block diagram of a conventional transceiver device 1. A bus BUS- which is pulled-up to potential VD and a bus BUS+ which is pulled-down to potential VS, which form a LAN transmission line 300 as a pair, are connected to the transceiver device 1 through terminals 14 and 13, respectively. The transceiver device 1 also has a terminal 9 to which input data TX to be provided to the buses BUS+ and BUS-, a terminal 10 for transmitting abnormalities in the buses BUS+ and BUS-, and a terminal 11 for transmitting data which have been provided to the buses BUS+ and BUS-.
A driver circuit 2 is connected to the terminals 13 and 14 to give input data to the LAN transmission line 300 (the BUS+ and the BUS-). An output control circuit 3 is connected to the terminal 9 and controls driving of the driver circuit 2 according to the input data TX. A bus input circuit 4 is connected to the terminals 13 and 14, which transmits the data provided to the buses BUS+ and BUS- to the terminal 11 through an input select circuit 6.
The data provided to the buses BUS+ and BUS- are converted into signals VO, VM, VP in the bus input circuit 4, and provided to an abnormality detecting circuit 5 connected to the terminal 10 and also to a reset circuit 8. If an abnormality occurs on the buses BUS+ and BUS-, the abnormality detecting circuit 5 transmits the abnormality to the terminal 10. However, in normal cases, a signal indicating abnormality is not given to the terminal 10 because the reset circuit 8 continues resetting the abnormality detecting circuit 5.
If an abnormality takes place on one of the LAN transmission line, i.e., one of the buses BUS+ and BUS-, the input select circuit 6 selects and outputs output data given to a bus which is operating normally. For this purpose, the input select circuit 6 is also connected to the abnormality detecting circuit 5.
FIG. 41 is a circuit diagram showing a specific circuit configuration of a part of the transceiver device 1 shown in FIG. 40, that is, the driver circuit 2, the output control circuit 3, the bus input circuit 4, the abnormality detecting circuit 5 and the reset circuit 8.
The output control circuit 3 includes a flip-flop F1 and gates G1 and G3. The gate G1, being controlled by a stand-by signal STB outputted from a stand-by control circuit 7, receives input data TX provided to the terminal 9. Receiving the input data TX, the output control circuit 3 drives the driver circuit 2, and a signal corresponding to the input data TX is transmitted to the buses BUS+ and BUS- through the terminals 13 and 14.
The driver circuit 2 includes a PMOS transistor P1, an NMOS transistor N1, and an inverter I1. Potential VD is applied to a source of the PMOS transistor P1, of which drain is connected to the terminal 13. Also, potential VS is applied to a source of the NMOS transistor N1, of which drain is connected to the terminal 14. Accordingly, the PMOS transistor P1 drives the bus BUS+ so that it is in the same phase as the input data TX and the NMOS transistor N1 drives the bus BUS- with the opposite phase to the input data TX.
The bus input circuit 4 includes a comparator CP for comparing the data provided to the bus BUS+ and a reference potential VR to obtain a signal VP, a comparator CM for comparing the data given to the bus BUS- and the reference potential VR to obtain a signal VM, and a comparator CO for obtaining a differential signal VO of the data given to the buses BUS+ and BUS-.
The reference potential VR is normally set to potential (VD+VS)/2. The signal VP attains "H" if the potential of the data given to the bus BUS+ is larger than the reference potential VR, and attains "L" if it is smaller than that. The signal VM attains "H" if the potential of the data given to the bus BUS- is smaller than the reference potential VR, and attains "L" if it is larger than that. Also, the signal VO attains "H" if the potential of the data given to the bus BUS+ is larger than the potential of the data given to the bus BUS-, and attains "L" if it is smaller. Accordingly, if the buses BUS+ and BUS- are normal, these three signals VP, VO and VM are in-phase to each other.
The abnormality detecting circuit 5 includes T flip-flops TP1 and TP2 for counting the signal VP, a D flip-flop DP for latching output of the flip-flop TP2, T flip-flops TM1 and TM2 for counting the signal VM, a D flip-flop DM for latching output of the flop-flop TM2, and an NAND gate G0 for taking a logical sum of outputs of the D flip-flops DP and DM.
Outputs of the D flip-flops DP and DM are signals DPQ and DMQ obtained by latching and inverting outputs of the flip-flops TP2 and TM2, respectively, which are transmitted to the input select circuit 6.
The input select circuit 6, although it is not shown in detail, transmits the signal VO to the terminal 11 when the LAN transmission lines operate normally, or when normal data are given to the LAN transmission lines. If an abnormality takes place, for example, if one of the buses BUS+ and BUS- is shorted to the potential VS or VD, the input select circuit 6 receives the signal DPQ, DMQ outputted by the abnormality detecting circuit 5 and selects a signal applied to a normal bus and transmits it to the terminal 11.
Now, the operation of the abnormality detecting circuit 5 at the time when the bus BUS+ is shorted to the potential VS is considered as an example. The signal VP falls to "L" and fixed at the state. Since the bus BUS- is operating normally, normal potential is given to the terminal 14. In the potential given to the terminal 14, however, a voltage decrease is normally caused by on-resistance of the transistor N1, so that it does not decreases to the potential VS. Accordingly, if the bus BUS+ is shorted to the potential VS, even when the bus BUS- becomes the "L" level, the potential appearing at the terminal 13 is lower. Therefore, the differential output VO is also fixed at "L".
Accordingly, as will be described later, the reset circuit 8 does not provide the reset signal RST to the abnormality detecting circuit 5. As a result, reset is not performed for the flip-flops TP1, TP2, DP, TM1, TM2 and DM which are to be reset with the reset signal RST in normal operation, and counting by these flip-flops is started.
On the other hand, since the signal VP is fixed at "L", the flip-flops TP1, TP2 and DP do not operate. The signal VM transfers potential corresponding to data given to the bus BUS- and its fall is counted by TM1 and TM2 which started counting. Then at the fourth fall of the signal VM, the flip-flop DM operates and the signal DMQ attains "L". This is transmitted to the input select circuit 6 to transmit an abnormality on the bus BUS+.
In the same way, the signal DPQ attains "L" if an abnormality takes place on the bus BUS-, and the abnormality is transmitted to the input select circuit 6. Inversion of the logical sum of the signals DPQ and DMQ is outputted from the gate G0 as a signal ERR, and the signal ERR is transmitted to the terminal 10 and the output control circuit 3. In the output control circuit 3, when the error signal ERR attains "L", the flip-flop F1 is reset. The output of the gate G3 attains "H" accordingly, and the driver circuit 2 is turned off.
The reset circuit 8 includes inverters I2-14 for generating a reset signal RST which is negative pulse with a fall of the signal VO, a NAND gate G4 and capacitor C. The reset signal RST is supplied to reset terminals R of the flip-flops TP1, TP2, DP, TM1, TM2, and DM included in the abnormal detecting circuit 5 through the AND gate G2, and these flip-flops are continuously reset as long as the signal VO provides normal potential changes. If the potential given by the signal VO is fixed, however, the reset signal RST does not reset these flip-flops as described above. A power-supply reset circuit ROP is connected with the AND gate G2 to generate a reset signal RST also at turn-on of power-supply.
After the error signal ERR is once outputted as "L", if the buses BUS+, BUS- are recovered from the abnormality and normal data is applied to the same, the differential output VO gets out of the fixed state. Thus, the reset signal RST is supplied to the reset terminals R of the flip-flops TP1, TP2, DP, TM1, TM2 and DM in the abnormality detecting circuit 5. That is, the reset signal RST is outputted at the first rise of the signal VO, and all the flip-flops in the abnormality detecting circuit 5 are reset. Accordingly, the error signal ERR also attains "H".
When the error signal ERR attains "H", the flip-flop F1 of the output control circuit 3 moves from the reset state to the operable state, and the gate G3 opens with a rise of input data applied to the terminal 9 and the like. Subsequently, the driver circuit 2 operates corresponding to the input data.
In the conventional art, if an abnormality takes place only on one of a pair of transmission lines, the data applied to the other normal transmission line is inputted to the transceiver device, but input data can not be applied even to the other transmission line because the driver circuit is turned off. Accordingly, when constituting a network with a plurality of units through the pair of transmission lines, there was the first problem that all the units turn off if an abnormality occurs on one of the pair of transmission lines, with the result that the mutual communications become impossible.
Furthermore, when the mutual communications once became impossible, since no unit supplies data to the transmission lines, processings for the error provided to the output control circuit is not canceled even if the transmission line has recovered from the abnormality. Accordingly, there was the second problem that the power-supply must be turned on again to recover the driver circuit.
Also, in the conventional abnormality detecting circuit constituted as described above, when an abnormality takes place on one of the pair of transmission lines, the abnormality is not recognized until pulse comes to the other normal one four times or more. Therefore, there was the third problem that the first part of the data is not normally transferred even after the transmission line has recovered to the normal condition. It may cause a problem in some specifications of system.